[verilog] edge detector

module dual_edge_detect
(
  clk,
  signal,
  pulse
);
input clk;
input signal;
output pulse;

reg signal_prev;
always @(posedge clk)
  signal_prev <= signal;
assign pulse = (~signal & signal_prev) | (signal & ~signal_prev); 
endmodule



module rising_edge_detect
(
  clk,
  signal,
  pulse
);
input clk;
input signal;
output pulse;

reg signal_prev;
always @(posedge clk)
  signal_prev <= signal;
assign pulse = signal & ~signal_prev;
endmodule



module falling_edge_detect
(
  clk,
  signal,
  pulse
);
input clk;
input signal;
output pulse;
reg signal_prev;
always @(posedge clk) 
  signal_prev <= signal;
assign pulse = ~signal & signal_prev;
endmodule