I coded this algorithm using a verilogHDL and I designed a combinational logic. so you can change the design using a sequential logic and pipeline architecture.
/*
* exp(k)
* 5.5452 256
* 2.7726 16
* 1.3863 4
* 0.6931 2
* 0.4055 3/2
* 0.2231 5/4
* 0.1178 9/8
* 0.0606 17/16
* 0.0308 33/32
* 0.0155 65/64
* 0.0078 129/128
*
* 32bit
* fix point
* 16bit.16bit
* */
module fxexp(
x,
y
);
input [31:0] x;
output [31:0] y;
wire [31:0] tmp0,tmp1,tmp2,tmp3,tmp4,tmp5,tmp6,tmp7,tmp8,tmp9,tmp10;
wire [31:0] tmp_x0, tmp_x1, tmp_x2, tmp_x3, tmp_x4,
tmp_x5, tmp_x6, tmp_x7, tmp_x8, tmp_x9, tmp_x10;
wire [31:0] tmp_y0, tmp_y1, tmp_y2, tmp_y3, tmp_y4,
tmp_y5, tmp_y6, tmp_y7, tmp_y8, tmp_y9,
tmp_y10,tmp_y11,tmp_y12,tmp_y13,tmp_y14,
tmp_y15,tmp_y16,tmp_y17,tmp_y18,tmp_y19;
assign tmp0 = x - 32'h00058b91;
assign tmp1 = tmp_x0 - 32'h0002c5c8;
assign tmp2 = tmp_x1 - 32'h000162e4;
assign tmp3 = tmp_x2 - 32'h0000b172;
assign tmp4 = tmp_x3 - 32'h000067cd;
assign tmp5 = tmp_x4 - 32'h00003920;
assign tmp6 = tmp_x5 - 32'h00001e27;
assign tmp7 = tmp_x6 - 32'h00000f85;
assign tmp8 = tmp_x7 - 32'h000007e1;
assign tmp9 = tmp_x8 - 32'h000003f8;
assign tmp10 = tmp_x9 - 32'h000001fe;
assign tmp_x0 = (tmp0[31]) ? x : tmp0;
assign tmp_x1 = (tmp1[31]) ? tmp_x0 : tmp1;
assign tmp_x2 = (tmp2[31]) ? tmp_x1 : tmp2;
assign tmp_x3 = (tmp3[31]) ? tmp_x2 : tmp3;
assign tmp_x4 = (tmp4[31]) ? tmp_x3 : tmp4;
assign tmp_x5 = (tmp5[31]) ? tmp_x4 : tmp5;
assign tmp_x6 = (tmp6[31]) ? tmp_x5 : tmp6;
assign tmp_x7 = (tmp7[31]) ? tmp_x6 : tmp7;
assign tmp_x8 = (tmp8[31]) ? tmp_x7 : tmp8;
assign tmp_x9 = (tmp9[31]) ? tmp_x8 : tmp9;
assign tmp_x10 = (tmp10[31]) ? tmp_x9 : tmp10;
assign tmp_y0 = 32'h00010000;
assign tmp_y1 = (tmp0[31]) ? tmp_y0 : {tmp_y0[23:0],8'h00};
assign tmp_y2 = (tmp1[31]) ? tmp_y1 : {tmp_y1[27:0],4'h0};
assign tmp_y3 = (tmp2[31]) ? tmp_y2 : {tmp_y2[29:0],2'b00};
assign tmp_y4 = (tmp3[31]) ? tmp_y3 : {tmp_y3[30:0],1'b0};
assign tmp_y5 = (tmp4[31]) ? tmp_y4 : (tmp_y4+tmp_y4[31:1]);
assign tmp_y6 = (tmp5[31]) ? tmp_y5 : (tmp_y5+tmp_y5[31:2]);
assign tmp_y7 = (tmp6[31]) ? tmp_y6 : (tmp_y6+tmp_y6[31:3]);
assign tmp_y8 = (tmp7[31]) ? tmp_y7 : (tmp_y7+tmp_y7[31:4]);
assign tmp_y9 = (tmp8[31]) ? tmp_y8 : (tmp_y8+tmp_y8[31:5]);
assign tmp_y10 = (tmp9[31]) ? tmp_y9 : (tmp_y9+tmp_y9[31:6]);
assign tmp_y11 = (tmp10[31]) ? tmp_y10 : (tmp_y10+tmp_y10[31:7]);
assign tmp_y12 = (tmp_x10[8]) ? (tmp_y11+tmp_y11[31:8]) : tmp_y11;
assign tmp_y13 = (tmp_x10[7]) ? (tmp_y12+tmp_y12[31:9]) : tmp_y12;
assign tmp_y14 = (tmp_x10[6]) ? (tmp_y13+tmp_y13[31:10]) : tmp_y13;
assign tmp_y15 = (tmp_x10[5]) ? (tmp_y14+tmp_y14[31:11]) : tmp_y14;
assign tmp_y16 = (tmp_x10[4]) ? (tmp_y15+tmp_y15[31:12]) : tmp_y15;
assign tmp_y17 = (tmp_x10[3]) ? (tmp_y16+tmp_y16[31:13]) : tmp_y16;
assign tmp_y18 = (tmp_x10[2]) ? (tmp_y17+tmp_y17[31:14]) : tmp_y17;
assign tmp_y19 = (tmp_x10[1]) ? (tmp_y18+tmp_y18[31:15]) : tmp_y18;
assign y = (tmp_x10[0]) ? (tmp_y19+tmp_y19[31:16]) : tmp_y19;
endmodule
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